Signal processing system

ABSTRACT

A system for data communication purposes in electronic devices comprises a data bus comprising first, second, third and forth signal paths. A first control means generates a first state of a control signal in the presence of a clock signal in a first mode of operation. The first operation mode may be the normal operation mode of a consumer electronic apparatus. A second control means generates a second state of the control signal in the presence of a clock signal in a second mode of operation. The second operation mode may be the stand-by mode of the consumer electronic apparatus. The system can be easily integrated into existing systems utilizing e.g. a VFD protocol.

The present invention involves signal processing system controlled via adata bus such as a serial data bus. Signal processing systems such asthose in consumer electronics devices typically include digitalintegrated circuits (ICs) that implement various functions. For example,in a television receiver, ICs provide signal processing functionsincluding tuning, video processing, and audio processing. In addition, amicrocomputer (μC) IC controls the operation of the other ICs by writingdata, such as control parameters, to the ICs and reading data, such asstatus data, from the ICs. Information is communicated between the ICsand the control μC via a data bus such as a serial data bus.

In EP 0 693 729 A1 a multi-protocol 3-wire data bus system is described.The known serial data bus system comprises a data bus including twoclock lines and a data line. A controller generates a first clock signal(SCL) and a first data signal (DATA) according to a first serial databus protocol (IIC) during a first mode of operation of the system, andgenerates a second clock signal (CLOCK) and a second data signal (DATA)according to a second serial data bus protocol (IM) during a second modeof operation. The first clock signal (SCL) and the first data signal(DATA) are provided on the first and third signal paths, respectively,during the first mode of operation. The second clock signal (CLOCK) andthe second data signal (DATA) are provided on the second and thirdsignal paths, respectively, during the second mode of operation.

The technical teaching of the multi-protocol data bus system cannot beapplied to a 4-wire data bus system operated by means of a protocolcalled a VFD protocol. A practical application of the VFD protocol ispresented in the following.

According to the European Regulation (IEC 60107-1(100 A/5FDIS)), thestand-by power consumption of consumer electronic devices like e.g. TVsor VCRs have to be reduced to a maximum of 5 Watt after Jan. 1, 2001, amaximum of 3 Watt after Jan. 1, 2003 and a maximum of 1 Watt after Jan.1, 2005. In principle it is possible to use a mechanical switch on thedevice to turn it into a complete “off” state, i.e. the device isentirely inoperative. Then, on the one hand the power consumption of thedevice is reduced to zero. On the other hand, it is not possible for theuser to conveniently turn the device again into the “on” state by aninfrared remote control because also the infrared receiver of the deviceinoperative.

In order to avoid this disadvantage the EP 0 158 251 A1 proposes tomaintain a remote control receiver in an operating state while the mainsystem is switched off.

The realisation of this general concept disclosed in EP 0 158 251 A1based on the VFD protocol for a 4-wire serial data bus requires anindependent communication channel between the main system and anauxiliary controller controlling the infrared receiver. However, whilethis approach provides the desired low energy consumption and userconvenience it increases the overall manufacturing costs of the system.

It is therefore desirable to suggest a signal processing system thatalleviates the above-mentioned limitations.

The invention proposes a signal processing system comprising a data buscomprising first, second, third and forth signal paths. A first controlmeans generates a first state of a control signal in the presence of aclock signal in a first mode of operation. The first operation mode maybe the normal operation mode of a consumer electronic apparatus. Asecond control means generates a second state of the control signal inthe presence of a clock signal in a second mode of operation. The secondoperation mode may be the stand-by mode of the consumer electronicapparatus.

In an advantageous embodiment of the invention the first control meansapply a VFD protocol in the first mode of operation. As control signal astrobe signal may be chosen.

The signal processing system according to the invention canadvantageously be integrated into any existing system, which has a VFDdriver for display. The basic idea of the invention is to have twological channels on only one physical wiring. There is no confusion inthe existing communication. For the extension of the existing VFDprotocol only two things have to be done:

Software has to be added for the sharing of communication hardwareinterfaces to communicate with the VFD driver and an auxiliary driver,which is operative during the stand-by mode. In addition the associatingprotocol for the auxiliary control has to be incorporated as well.Advantageously the existing 4-line connection can be used and noadditional line is necessary to incorporate the new operability. Theauxiliary driver is capable of performing sub-system control for themain system and the control message and acknowledgement message can bepassed through the associating protocol in full duplex way. Finally theprotocol can easily be adapted to any bit length message.

In the drawing an exemplary embodiment of the present invention isillustrated. It shows

FIG. 1 a system overview of a device comprising the inventive signalprocessing system;

FIG. 2 the data bus communication connection

FIG. 3 the data bus communication in the power-down mode;

FIG. 4 a flow diagram of the communication system;

FIGS. 5 and 6 waveforms illustrating operating modes of the signalprocessing system.

In FIG. 1 the general structure of a consumer electronics apparatus 1 isshown in a schematic way. The apparatus 1 is structured in a first and asecond portion 2, 3, which are both supplied with power from a mainpower line 4. The first portion 2 comprises a main system 6, which issupplied by a main power supply 7. The main system 6 may include themedia drives of a VCR or a DVD player, signal processing circuits etc.In any case the main system 6 includes all elements and componentsexhibiting a high power consumption.

The second portion 3 of the apparatus 1 comprises an auxiliarycontroller 8, a VFD driver 9 (e.g. the μPD16315 commercially availablefrom NEC Corporation), an IR receiver 11 and a stand-by power supply 12.The auxiliary controller 8 communicates with the VFD driver 9 via a4-wire serial data bus system. The stand-by power supply permanentlysupplies all elements of portion 3 with power as soon as the apparatus 1is connected to mains. In addition, the auxiliary controller 8 controlsa relay 13 to selectively turn on or off the main power supply 7 of theapparatus 1. In stand-by mode the relay 13 is not conducting and thepower consumption of the apparatus 1 is reduced to e.g. 1 Watt.

In FIGS. 2 and 3 the VFD communication connection is shown in greaterdetail.

In the power-up mode shown in FIG. 2 the auxiliary controller is workingas another VFD driver and connected in parallel.

The main system communicates with the VFD driver using original VFDprotocol and with controller using associating VFD protocol, which willbe described in greater detail below. The D_(out) of VFD driver must bean open-collector output. If not, additional interface logic must beadded.

In the power-down mode shown in FIG. 3 the auxiliary controller becomesa host to poll the key from the front panel and detect the key from IRremote receiver. It uses the original VFD protocol to receive the frontpanel key signal.

The bus attached to main system 6 is assumed to have high impedance whenthe auxiliary controller switches the main power supply off. Theauxiliary controller re-configures the I/O direction in the power-downand power-up mode.

The flow diagram in FIG. 4 illustrates the communication between theauxiliary controller 8 and the main system 6. The doted lines 14 a, 14 bin the diagram separate the hardware levels of the auxiliary controller8 and the main system 6 with the communication level in between. Thehorizontal doted lines 15 a, 15 b separate the two operating modes ofthe apparatus 1, i.e. power-up and power-down mode, respectively, and atransition mode between the two operating modes.

In FIG. 5 a typical example of a VFD protocol is shown, which uses astrobe STB signal and a clock CLK signal simultaneously to feed in thecommand or data into the VFD driver 9. The command is distinguished fromthe data by the first byte following the falling edge of the STB signal.As can be seen in FIG. 5 the STB signal is always low associated withclock signal to shift data to or from the VFD driver 9.

In the design of an associating VFD protocol several criteria must bemet:

The associating VFD protocol must not confuse the original VFD protocolin order to avoid any perturbation of the VFD driver in normaloperation. This is achievable if the VFD driver is arranged such that itcan easily ignore the associate protocol. The associating VFD protocolmust be easily distinguishable from the original VFD protocol by theauxiliary controller 8. And finally, the associating VFD protocol mustcontain a start signature (or header) to inform the auxiliary controller8 that it is his turn to exchange the data with main system. Of course,the VFD driver 9 ignores this signature and does not affect the incomingdata in the protocol.

In FIG. 6 the proposed associate VFD protocol is illustrated. In theassociate VFD protocol the strobe low signal before the clock signal isused as the start signature. It is important to note that on the onehand the strobe signal is always kept high in the presence of the clocksignal so that it will not affect the original VFD protocol. On theother hand, the auxiliary controller 8 can easily distinguish theoriginal VFD protocol by detecting the strobe signal in the presence ofthe clock signal whether the strobe signal keeps low, otherwise, it mustbe the associating VFD protocol.

In the original VFD protocol the strobe signal STB is low when a clocksignal CLK is present. In contrary, in the associating VFD protocol thestrobe signal STB is high when a clock signal CLK is present.

1. A signal processing system comprising: a data bus comprising first,second, third and fourth signal paths, first control means forgenerating a first state of a control signal in the presence of a clocksignal in a first mode of operation, and second control means forgenerating a second state of the control signal in the presence of aclock signal in a second mode of operation.
 2. System according to claim1, wherein the first control means applies a VFD protocol in the firstmode of operation.
 3. System according to claim 1, wherein the controlsignal is a strobe signal.